In one form of high density interconnect (HDI) circuit module, an adhesive-coated polymer film overlay having via openings covers a plurality of integrated circuit chips in chip wells on an underlying substrate. The polymer film provides an insulated layer upon which is deposited a metallization pattern for interconnection of individual circuit chips through the vias. Methods for performing a HDI process using overlays are further described in Eichelberger et al., U.S. Pat. No. 4,783,695, issued Nov. 8, 1988, and in Eichelberger et al., U.S. Pat. No. 4,933,042, issued Jun. 12, 1990. Multiple layers of polymer overlays and metallization patterns are typically applied, and significant processing steps are required to complete these multilayer interconnects.
Prefabricated flexible interconnect layers having metallization patterns thereon are manufactured by companies such as Sheldahl Corp., Northfield, Minn., and Parlex Corp., Methuen, Mass., for example. Multichip module and other electronic assembly manufacturers conventionally couple integrated circuit chips and other components to the metallization patterns using mechanical assembly attaching techniques such as wire bonding, tape automated bonding, or solder bumps. A prefabricated flexible interconnect structure typically has at least one insulative film layer having a thickness sufficient to support metallization patterns on each side. The thickness is often between 1 to 5 mils (25 to 125 microns).
Cole et al., "Fabrication and Structures of Circuit Modules with Flexible Interconnect Layers," U.S. application Ser. No. 08/321,346, filed Oct. 11, 1994, now U.S. Pat. No. 5,527,741 describes a method for fabricating a circuit module using a flexible interconnect layer including a metallized base insulative layer and an outer insulative layer. At least one circuit chip having chip pads is attached to the base insulative layer and vias are formed in the outer and base insulative layers to expose selected portions of the base insulative layer metallization and the chip pads. A patterned outer metallization layer is applied over the outer insulative layer extending through selected ones of the vias to interconnect selected ones of the chip pads and selected portions of the base insulative layer metallization.
The technique described in Cole et al. can lower the volume and weight of a circuit module. Because the coefficient of thermal expansion (CTE) of the chips is generally much less that the CTE of the flexible interconnect layer, however, if the area density of chips on the flexible interconnect layer is too high, unbalanced stresses and associated warping can occur.